Powering ADSL, New chip technology will reduce ADSL power consumption and cost >BY DEBBIE SALLEE and MATT PENDLETON

Asymmetrical digital subscriber line, a powerful transmission technology enabling an array of new broadband services, is about to debut in telephone networks around the world. ADSL delivers more than 6 Mb/s to the user and more than 640 kb/s back to the source over twisted pair copper wiring. As service providers prepare their networks to deliver faster Internet access and new interactive multimedia services via ADSL, power requirements and limitations are getting a lot of attention. The need for higher power means more cost for the service provider. Silicon providers are developing solutions that employ highly integrated mixed-signal and analog low-power designs.

ADSL basics For service providers, universal coverage of all customers is extremely important. In the U.S., two network configurations must be deployed for ADSL data service to reach all customers (Figure 1).

In the first configuration, ADSL is deployed from the central office. In this setup, an ADSL modem is installed at the customer premises. Each telephone line receiving ADSL service requires a dedicated ADSL line card, which is installed in a multiplexer at the CO.

In the CO, the POTS signal is separated from the rest of the signal and directed through the main switch, while the multiplexer-which is essentially a high-speed data router-handles the video and data services. ADSL data and video traffic is multiplexed together and routed out of the CO via a fiber distribution cable.

The Bell companies estimate that they can serve more than 80% of their customers from the CO using ADSL modems based on discrete multitone (DMT) technology.

For the unreachable 20%, fiber must be deployed to a digital loop carrier (DLC) system, from which customers are served over copper wire measuring 12,000 feet or less. The ADSL line card resides in the multiplexer in the DLC system.

This second network configuration can also be used to increase the bandwidth available to some of the customers in the reachable 80% because shorter distances between the customer and the line card equate to higher available data rates.

Typical power budgets for CO-based configurations are approximately 10 watts per line card. Because of its remote location and environment, target power budgets are approximately 3 to 4 watts per line card for the DLC configuration.

With both ADSL designs, fans are often necessary for proper cooling, and they add cost to the system. In DLC configurations, special housings and other methods are under investigation to compensate for the increase in power consumption.

Lowering the power dissipation of the ADSL silicon implementation-thus reducing or elim- inating the need for fans or other special cooling devices-is a major concern for service providers.

Early versions of ADSL modem chipsets required as much as 20 watts average per line. These systems were implemented with off-the-shelf digital signal processors and discrete analog components, resulting in costly and power-hungry modems that were never intended to be used for commercial deployment.

The industry has come a long way since then, and current systems have cut power consumption in half. Motorola's CopperGold ADSL system, which will be introduced in early 1997, will cut power consumption in half again-to less than 5 watts average power. Silicon vendors are racing to bring the cost and power consumption down even further as quickly as possible.

Balancing the design The goal for low power must be in balance with the goal for low cost. The lowest-power solution typically will not be the lowest-cost implementation.

Advanced digital communications integrated circuits that are used to implement ADSL transceivers employ a range of digital processing functions, such as Fast Fourier Transforms, fixed and adaptive digital filters, and signal coding. The major decisions facing systems designers are which functions should be implemented in dedicated hardware vs. software running on a programmable digital signal processor, and which functions are to be implemented in analog vs. digital.

A single function implemented in dedicated hardware will always use less power than a software solution. Before using dedicated hardware, however, designers should carefully consider the accompanying loss of flexibility to the system and increased silicon cost. Using a mixture may be the best solution: Custom hardware can be employed for operation-intensive, fixed functions, and software can be used for initialization and less intensive operations.

Digital designs require less power than analog designs and will benefit the most from tomorrow's advances in manufacturing processes. Switching transistors that are used to represent logical ones and zeros in the digital domain may be shrunk to the limit defined by a company's manufacturing capability.

Once the hardware-vs.-software and digital-vs.-analog decisions have been made, designers turn their attention to the partitioning of the silicon. The challenge is to decide what to include and what not to include on the same piece of silicon (Figure 2).

Taking a function off-chip increases power because of the large capacitance of pads and printed circuit board traces. To reduce the number of system devices-and integrate as many functions as possible onto one piece of silicon while balancing the need for flexibility-Motorola's systems designers partitioned the CopperGold ADSL system into a single transceiver, a line driver and a host controller.

An ongoing process Because power is proportional to the square of the supply voltage, the greatest power savings can be made by simply reducing this voltage. Lowering the supply voltage, however, reduces the speed at which the device transistors switch, potentially requiring more operations to be performed in parallel and increasing the number of transistors.

This effect can be mitigated by the judicious use of custom circuitry in place of standard cells. Custom circuitry will operate faster and consume less power but will take longer to design. For the less speed-intensive circuits, standard cells may be used, especially if the standard cell library itself is optimized for low-power circuits.

Other circuit design practices that can help ensure low-power requirements include using fully static logic, employing on-chip phase lock loops to keep external clocks at the lowest possible frequency, and most importantly, avoiding needless clocking when circuitry is not in use.

After an ADSL transceiver is designed, its manufacturing processes should be continuously reviewed with an eye toward further power reduction and cost savings. At events such as Motorola's annual War-On-Current Drain Symposium-an internal conference that focuses on power in silicon design and manufacturing-engineers discuss the latest in tools, techniques and processes for lower-power silicon solutions.

Service providers reap the benefits of good silicon design over time. The cost of ADSL prototype modems was tens of thousands of dollars per line. Today, most modems are available for a few thousand dollars per line. The target cost is less than $500 per line.

Recognizing that cost and power goals for equipment are tightly coupled with advances in silicon designs, service providers are anxiously watching silicon developments for ADSL systems.

As higher levels of integration are reached through good systems, architecture, and circuit design-along with the added benefit of improvements in the manufacturing process-the effect on the cost and power of the ADSL modem equipment will be dramatic. Potentially, multibillion-dollar revenue streams for interactive multimedia services are at stake.

Debbie Sallee is ADSL Business Development Manager for Motorola Semiconductor, and Matt Pendleton is ADSL Design Manager for Motorola Semiconductor's Wireline IC Division, Austin, Texas. Their e-mail addresses are rzep90 @email.mot.com and matt_pendleton@email.

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