The jitter bug

Interoperability is touching every aspect of the telecom industry, and Sonet is no exception. The jitter specifications of the physical interface connecting Sonet equipment are an often overlooked yet vital requirement for interoperability.

Why must Sonet equipment meet jitter requirements? Why are jitter requirements important to equipment interoperability? The answers to these questions are important to network design and implementation.

First, what is jitter? Discussions on clock recovery and clock synchronization assume an ideal world. In real-world applications, the incoming data signal will not be transitioning at exactly the same time interval every bit-time. The transition or bit period of the data signal can be slightly shorter or longer than the ideal period. This displacement of digital transition is called jitter. Jitter has numerous causes and components that are both deterministic and random.

In an asynchronous network, digital transitions of the signals within the network do not necessarily occur at the same rate. For example, if two signals in a network are clocked by two free-running crystal oscillators, those signals will be transmitted at different frequencies and phases. If one system is running at 1 Mb/s and another system is transmitting 40 p/m faster (at 1 b/s * [1+40*10^6] = 1.000040 Mb/s), the slower system will lose 40 bits of data every second.

Sonet is a synchronous network. In such a network, digital transitions of the signals within the network occur at exactly the same rate. This implies that the clocking signals at each transmit interface must run at the same rate. Although the clock rates are the same, a phase difference may exist between the two transmit signals. These phase differences could be caused by propagation delay through a cable or by jitter on the transmitted signal. Sonet jitter requirements limit these phase differences.

A matter of timing In the WAN, the Sonet building blocks, known as the Sonet network elements, include the terminal multiplexer, regenerator, add/drop multiplexer (ADM) and digital cross-connect system.

The terminal multiplexer acts as the entry point to the Sonet network. It concentrates lower rate tributary signals into higher rate Sonet payload. The tributary signals are usually DS-1 or DS-3 signals but also can be asynchronous transfer mode traffic.

The regenerator repeats the Sonet signals and extends cable distance between two Sonet network elements. The ADM does the same thing as a terminal multiplexer but adds the functionality of a regenerator. ADMs usually are used in a ring or a linear multi-drop network.

Finally, the DCS takes in multiple Sonet signals and switches the information between the two systems. The systems also can be used to mesh different Sonet rings together or to create other network configurations and provide fault tolerance.

All network elements must be synchronized to a highly stable timing reference. The Sonet standard defines several timing modes, and Sonet equipment must be capable of two or more of these timing modes.

External timing mode requires direct timing from a building integrated timing supply (BITS), which must meet Stratum 3 (+/-4.6 p/m) accuracy or better. A stratum clock is an accurate timing source from which the entire network is synchronized.

The DCS is required to support external timing. Line-timing mode requires the network element to derive the clock from a single incoming OC-N signal and use it for outgoing signals. This timing mode is used by all Sonet network elements except regenerators. Line-timing mode enables the network elements to synchronize to a single timing source.

Loop-timing mode is a special type of line-timing mode. It applies only to network elements with one Sonet interface, such as terminal multiplexers. Through-timing mainly applies to regenerators. The clock is derived from each incoming OC-N signal and is used as the transmit clock for the corresponding outgoing OC-N signal.

Another timing mode is free-running mode, in which outgoing network element signals are referenced to an internal clock. The internal clock must have an accuracy of +/-20 p/m. Free-running mode is used when the incoming OC-N signal, which is used as a timing reference, is not available. Sonet network elements must be capable of free-running mode.

For equipment capable of line-timing, loop-timing and through-timing modes, the derived clock for outgoing signals must meet the jitter specifications.

LAN ATM is the main reason Sonet interfaces are used in LANs. ATM has lost the battle to 100 Mb Ethernet as the primary protocol to the desktop, but ATM interface use is still growing in other parts of the LAN.

ATM connects data or application servers to the backbone. ATM switches make up part of the enterprise backbone to relieve traffic congestion. Ethernet hubs or switches have ATM up-links to backbone ATM switches. Besides traditional packet data applications in the LAN, ATM also can carry voice and video data, which may bring ATM into the home.

Ironically, the physical interface of an ATM port is by no means asynchronous. The ATM Forum chose Sonet to be one of the physical transport protocols for carrying ATM cells. Sonet has been the most popular physical transport protocol because of its well-defined operational, administration and management functions.

In LANs, the distance between Sonet interfaces is much smaller (within 100 m). Signals are transmitted over either Category 5 unshielded twisted pair cables or multimode optical fiber.

The basic network configuration of ATM LAN is a star topology in which the ATM switch resides at the center of the LAN and acts as the information hub.

All the servers or Ethernet hubs connect to the ATM switch via network interface cards (NICs). The cards run in loop-timing mode in which the primary clock source comes from the ATM switch. The ATM Forum specifies the frequency accuracy of network equipment-for example, an ATM switch-as +/-20 p/m. For free-running NICs, the transmit clock requirement is relaxed to +/-100 p/m.

The cabling and operating environment of ATM LAN equipment differs from WAN equipment. The ATM Forum has defined a set of jitter specifications for signals transmitted over category 5 unshielded twisted pair cable. For signals transmitted over optical fiber, the ATM Forum adheres to Sonet jitter requirements.

Bellcore jitter specifications The Sonet standard specifies jitter in three modes: jitter generation, jitter transfer and jitter tolerance. All WAN equipment capable of through-timing and line-timing modes must meet all three specifications to be considered Bellcore-compliant.

LAN equipment that runs in both free-running (ATM switch) and loop-timing modes with optical interfaces must meet jitter generation and jitter tolerance specifications to comply with the ATM Forum specification. These specifications are for equipment, not for the individual circuit or component.

Jitter generation identifies the amount of jitter that a serial interface can add to a data signal, assuming the reference clock is stable.

The Sonet specification limits this to 0.1 unit intervals for all jitter frequencies above 10 Hz. Jitter frequencies below 10 Hz are assumed to be "wander" and are ignored.

Jitter transfer is a combined specification that sets limits on the spectral characteristics of jitter that can be added to a signal as it passes through the equipment. Unlike the jitter generation specification, in which a high-stability reference clock is used, jitter transfer assumes that the transmit clock is derived from an incoming data stream, which often contains significant jitter components. This specification limits how much of the jitter may be passed to a new or repeated serial data stream (Figure 1).

Jitter tolerance specification identifies how much jitter a serial receiver interface must be able to accept while still recovering data within the bit error rate (BER) limits of the link. The Sonet standard limits the BER to IE-10 (1 x 10-10). The receiver's jitter tolerance must be significantly greater than the combined jitter generation of the source and the media. The more jitter the receiver can withstand while recovering data correctly, the better the receiver (Figure 2).

Equipment with Sonet interfaces must meet the jitter generation and jitter tolerance requirements. Only equipment capable of line-timing and through-timing must meet the additional jitter transfer specification, because when equipment is running in line-timing and through-timing mode, excessive jitter on an incoming signal must be filtered before passing onto the equipment downstream. Equipment running in loop-timing mode does not need to meet the transfer requirement because the receiver of the equipment's transmitted data is the clock source for the transmit clock.

WAN equipment must be capable of free-running mode, unless a BITS is available. The equipment also must support either line-timing or through-timing mode. Therefore, WAN equipment must meet all three jitter requirements. For LAN equipment, NICs run in loop-timing mode, acting as a timing slave to the switch, and the switch is free-running unless one of its ports is connected to the WAN. Therefore, LAN equipment must satisfy only the jitter generation and jitter tolerance specifications.

In the case of an ATM switch with one or more ports connected to the WAN, the switch derives its transmit clocks from the incoming WAN data stream, so it runs in line-timing mode. This edge switch must satisfy the jitter transfer requirement as well as jitter generation and jitter tolerance requirements.

Bellcore-compliant systems Only data is communicated over Sonet links in both LANs and WANs. The derivation of clock from an incoming data signal is done by a special piece of circuitry called the clock and data recovery (CDR) device.

Figure 3 shows a Sonet line interface card. The CDR sits between the media driver and the Sonet frame processing logic. The CDR consists of high performance phase-locked loops that perform clock extraction,data recovery and clock multiplication (Figure 4).

Jitter generation relates to both the transmit clock multiplier phase-locked loop and the receiver phase-locked loop. In line-timing mode, a stable clock reference distributed from either a BITS or filtered recovered clock is used by a transmit clock multiplier phase-locked loop to generate a bit clock. In through-timing mode, a regenerator uses the recovered clock directly to transmit data. The jitter generated by these phase-locked loops is usually less than 0.005 UI-rms.

Two types of CDRs are available to system designers: one with a narrow bandwidth jitter transfer function phase-locked loop and one with wide bandwidth. Figure 5 shows the jitter transfer characteristics of both.

The transfer function of the narrow bandwidth CDR stays within the Bellcore jitter transfer specification limit while the wide bandwidth CDR exceeds the critical frequency limit.

The narrow bandwidth CDR is the best candidate for implementing jitter transfer-compliant systems, but there are trade-offs. As the phase-locked loop bandwidth decreases, so does its capability to respond. A narrow bandwidth phase-locked loop takes longer to lock onto a data stream and will not handle as much jitter in some spectral ranges compared with the wide bandwidth phase-locked loop.

Figure 6 shows jitter tolerance characteristics for a wide bandwidth (CY7C951) and narrow bandwidth (CY7C952) CDR. The narrow bandwidth CDR still exceeds the Bellcore jitter tolerance requirement, while the wide bandwidth CDR can tolerate nearly an order of magnitude more jitter than required.

Wide and narrow bandwidth CDR circuits can be used to meet Sonet jitter tolerance requirements. The wide bandwidth CDR offers enhanced jitter tolerance and faster locking in many applications.

Faster tracking, lower transfer The desire for both faster jitter tracking (higher jitter tolerance) and lower jitter transfer bandwidth is orthogonal. At first glance there seems to be no right answer in choosing a CDR circuit. So to solve this paradox, the problem must be examined at the system level instead of just on the CDR.

Most WAN Sonet equipment contains a clock multiplexer board that replicates one clock source to multiple output ports on the equipment. The replicated clock may come from either an internally or externally referenced BITS or may be derived from a received data stream.

To ensure that this clock does not introduce extraneous jitter components to the system clock, it is usually filtered through a voltage-controlled crystal oscillator. The oscillator has very low transfer bandwidth and filters higher frequency jitter components. As a result, a wide bandwidth CDR is the better choice because it provides improved jitter tolerance characteristics. Wide bandwidth CDR is also suitable for LAN equipment.

NICs and LAN switches run in only two timing modes-loop-timing and free-running. Jitter transfer requirements do not need to be met in these modes.

Narrow bandwidth CDRs fit into signal regenerator and WAN ports of edge switches. These regenerators and edge switches can be built using wide bandwidth CDR and a secondary voltage-controlled crystal oscillator for filtering, but the cost can be prohibitive.

Unlike ADMs that can share a single voltage-controlled crystal oscillator with multiple line interfaces, regenerators must recover timing independently on each line interface. This is important because competition in LAN equipment is cost-driven.

Equipment with Sonet interfaces must meet the Sonet jitter specifications. The types of timing modes that the equipment supports mandate the jitter requirements that it must satisfy.

Systems that are not capable of line-timing and through-timing do not need to meet the jitter transfer requirement. The requirement does not limit the type of CDR a system can use. All three categories of jitter requirements can be met by using narrow bandwidth CDR circuits, which are targeted at cost-sensitive applications.

Wide bandwidth CDR circuits still can be used in systems that need to meet the jitter requirements; they require low bandwidth voltage-controlled crystal os cillator-filtering to meet the jitter transfer specification. On the other hand, they provide better jitter tolerance. In the end, the final goal of meeting these stringent requirements is to achieve equipment interoperability and network synchronization.